[PATCH] D99026: [RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64

Sat Mar 20 13:24:01 PDT 2021

craig.topper added a comment.

In D99026#2639790 <https://reviews.llvm.org/D99026#2639790>, @jrtc27 wrote:

> In D99026#2639788 <https://reviews.llvm.org/D99026#2639788>, @craig.topper wrote:
>
>> In D99026#2639787 <https://reviews.llvm.org/D99026#2639787>, @jrtc27 wrote:
>>
>>> I think the final line of your commit message is the wrong way round?
>>
>> Maybe it was poorly written. How does it look now?
>
> Ah that makes more sense, I misunderstood what your point was

I guess maybe we shouldn’t do this with Zba which has zext.w. Unless we know the ‘and’ is only used by the mul.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99026/new/

https://reviews.llvm.org/D99026