[PATCH] D98801: [NFC][RISCV] Wrong stack slot for GPR and RVV spilled registers

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 updated this revision to Diff 331545.
rogfer01 added a comment.

ChangeLog:

- Simplify the MIR input
- Split test in two for RV32 and RV64


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98801/new/

https://reviews.llvm.org/D98801

Files:
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D98801.331545.patch
Type: text/x-patch
Size: 3342 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210318/df402c4e/attachment.bin>