[PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.

[Zakk Chen via Phabricator via llvm-commits]

khchen added a comment.

> I'm slightly concerned that the upper bits of of the FPR are garbage so this might be a valid float value or it might be NaN.

IIUC, psabi <https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-hardware-floating-point-calling-convention> already has a rule for upper bits of the FPR?
`When a floating-point argument narrower than FLEN bits is passed in a floating-point register, it is 1-extended (NaN-boxed) to FLEN bits.`


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https://reviews.llvm.org/D98670