[PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.

[Craig Topper via Phabricator via llvm-commits]

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Without Zfh the half type isn't legal, but it could still be
used as an argument/return in IR. Clang will not generate this today.

Previously we promoted the half value to float for arguments and
returns if the F extension is enabled but Zfh isn't. Then depending on
which ABI is enabled we would pass it in either an FPR or a GPR in
float format.

If the F extension isn't enabled, it would get passed in the lower
16 bits of a GPR in half format.

With this patch the value will always in half format and will be
in the lower bits of a GPR or FPR. This should be consistent
with where the bits are located when Zfh is enabled.

I've based this implementation off of how this is done on ARM.

I'm slightly concerned that the upper bits of of the FPR are
garbage so this might be a valid float value or it might be NaN.
It looks like flw, fsw, fmv.s, fmv.w.x, fmf.x.w won't
canonicalize nans so should leave the value alone. I think those
are the instructions that could get used on this strange value.

This probably needs more tests to test the different ABIs,
running out of FPRs, running of GPRs, etc. I've done some spot
checking and everything looks ok so far. I'll add some directed
tests in the next day or two unless anyone has objections to this
patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98670

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/copysign-casts.ll

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