[PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 331304.
craig.topper added a comment.

NaN-box the value before putting it into a float register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98670/new/

https://reviews.llvm.org/D98670

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/copysign-casts.ll

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