[PATCH] D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

Wed Mar 17 07:53:10 PDT 2021

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

In D98501#2631735 <https://reviews.llvm.org/D98501#2631735>, @khchen wrote:

> I think it's shouldn't be generated and we noted them when we start working on supporting rvv intrinsics.
>
> Maybe we could define the explicitly type for vector/vector and vector/scalar in the IR intrinsic, it would make intrinsics more strongly typed.
> But personally I prefer to keep current intrinsic design...

Yeah fair enough, I see the issue. I don't propose we change the intrinsic design. I was also generating intrinsics at some point and was having difficulty determining which types to provide, as it tends to just crash when you get it wrong.

Ideally we'd have a check in the backend that the types are as we expect. Either explicit (asserts) or implicit (it doesn't select).

But all of that is increasing the scope of this patch, and this patch is already slowing down my browser, so let's get it in sooner rather than later :)

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