[PATCH] D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

[Zakk Chen via Phabricator via llvm-commits]

khchen added a comment.

In D98501#2622189 <https://reviews.llvm.org/D98501#2622189>, @frasercrmck wrote:

> I can see that the shift amount should be XLen, but is there a crash that this fixes? Or is it that it shouldn't be possible to generate these intrinsics in the first place? I'm wondering what (if anything) can be put in place to stop this from happening again.

I think it's shouldn't be generated and we noted them when we start working on supporting rvv intrinsics.

Maybe we could define the explicitly type for vector/vector and vector/scalar in the IR intrinsic, it would make intrinsics more strongly typed.
But personally I prefer to keep current intrinsic design...


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