[PATCH] D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

[Zakk Chen via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9998b00c2ecd: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D98501?vs=330224&id=331318#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98501/new/

https://reviews.llvm.org/D98501

Files:
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll