[PATCH] D98460: [RISCV] Add support for scalable vector masked load/store.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

In D98460#2622351 <https://reviews.llvm.org/D98460#2622351>, @craig.topper wrote:

> I couldn’t find a combine in DAGCombiner.cpp. As far as I could tell they can only be generated by the type legalizer. I think the fractional LMUL types mean we never Promote any i8/i16/i32 types so we won’t create an extending load or truncating store.

Fair enough, that's what I've seen with scatter/gather too.

Anyway, LGTM. Do all-true masks get auto-optimized to regular loads, even for scalable vectors?


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