[PATCH] D98460: [RISCV] Add support for scalable vector masked load/store.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D98460#2622098 <https://reviews.llvm.org/D98460#2622098>, @frasercrmck wrote:

> What happens for truncating stores, extending loads, etc? For example, does DAGCombine combine `masked.load+sext` by default or is it opt-in?

I couldn’t find a combine in DAGCombiner.cpp. As far as I could tell they can only be generated by the type legalizer. I think the fractional LMUL types mean we never Promote any i8/i16/i32 types so we won’t create an extending load or truncating store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98460/new/

https://reviews.llvm.org/D98460