[PATCH] D98174: [MCA] Add tests for IPC on Cortex-A55

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Any chance we can use more descriptive testcases names? :-)



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Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4.s:6-7
+# FIXME: DIV is not modeled precisely: on hardware it takes variable
+# number of cycles depending on its operands. LLVM scheduling model
+# only provides an average latency.
+#
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andreadb wrote:
> Not sure if it might help in this case, but in general I recommend to have a look at whether some operand constraints might be defined using MCSchedPredicate defs in SchedWriteVariant.
Is this something that is fixable in llvm? I thought it would not, in general, know the input value for an instruction.


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