[PATCH] D97316: AMDGPU: Add even aligned VGPR/AGPR register classes
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 23 12:39:07 PST 2021
rampitec added a comment.
I do not think it will help. There will be the same issue as with reserved registers. Assume you have VReg_128_align2. For sure RA will allocate an aligned register. But something like coalescer will happily use sub1_sub2 on it and you will end up with an unaligned physreg at the end. To make this working you need to make sure these registers do not have unaligned subregs.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:11586
+ default:
+ return -1;
+ }
----------------
llvm_unreachable?
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https://reviews.llvm.org/D97316/new/
https://reviews.llvm.org/D97316
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