[PATCH] D97316: AMDGPU: Add even aligned VGPR/AGPR register classes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kzhuravl.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
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gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

      

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).


https://reviews.llvm.org/D97316

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
  llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
  llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
  llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
  llvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
  llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
  llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir

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