[PATCH] D97021: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM otherwise.



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Comment at: llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll:6
+; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
+; for these intrinsics.1
+
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Stray `1` at the end here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97021/new/

https://reviews.llvm.org/D97021