[PATCH] D97021: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

[Craig Topper via Phabricator via llvm-commits]

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Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97021

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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