[PATCH] D97021: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdbf910f0d950: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D97021?vs=324849&id=325026#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97021/new/

https://reviews.llvm.org/D97021

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97021.325026.patch
Type: text/x-patch
Size: 16237 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210219/067caaa5/attachment.bin>