[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Thanks for pre-committing the test cases, I think it's cleaner now.

There's one comment I left but apart from that LGTM.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2692
+// Matches patterns of the form
+//   (and (shl x, C2), (C1 << 1))
+//   (and (srl x, C2), C1)
----------------
Should `1` be `C2` here and in the last line?


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  https://reviews.llvm.org/D96661/new/

https://reviews.llvm.org/D96661