[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG98dff5e80422: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D96661?vs=324694&id=325025#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96661/new/

https://reviews.llvm.org/D96661

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64Zbp.ll

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