[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I've pre-committed the test changes where I changed the OR operand order.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2523
     return None;
-
-  // These are the unshifted masks which we use to match bit-manipulation
-  // patterns. They may be shifted left in certain circumstances.
-  static const uint64_t BitmanipMasks[] = {
-      0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL,
-      0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL,
-  };
-
-  unsigned MaskIdx = Log2_64(ShAmt);
-  if (MaskIdx >= array_lengthof(BitmanipMasks))
+  // If we don't have enough masks for 64 bit, then we must be trying to
+  // match SHFL so we're only allowed to shift 1/4 of the width.
----------------
frasercrmck wrote:
> This bit seems specific to SHFL in a roundabout way. Is there a way to make it more generic, or at least explicit? I know we're only matching GREV or SHFL so we can expect certain preconditions but I worry it'd catch someone out if they wanted to use this method for other purposes.
I've updated the header to provide a better description. We could add another parameter to make it explicit, but I figured the caller already had to size the array of expected masks correctly.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96661/new/

https://reviews.llvm.org/D96661