[PATCH] D97020: [RISCV] Remove redundant test cases for index segment load (1/8).

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa32c79ce2c35: [RISCV] Remove redundant test cases for index segment load (1/8). (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97020/new/

https://reviews.llvm.org/D97020

Files:
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll