[PATCH] D97020: [RISCV] Remove redundant test cases for index segment load (1/8).

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

I verified that the number of tests now match the number of C intrinsics defined here https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_intrinsic_funcs/03_vector_load_store_segment_instructions_zvlsseg.md#vector-indexed-segment-load-functions minus intrinsics that require i64 which we aren't testing on rv32.

LGTM


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  https://reviews.llvm.org/D97020/new/

https://reviews.llvm.org/D97020