[PATCH] D96980: [amdgpu] Revert agnostic SGPR spill.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

In D96980#2572918 <https://reviews.llvm.org/D96980#2572918>, @arsenm wrote:

> Conflicts with D96336 <https://reviews.llvm.org/D96336>/D96517 <https://reviews.llvm.org/D96517>

Just have a detailed look of that two. Shall we optimize the case where 1 or 2 SGPRs need spilling/reloading and there's a scavenged register available. For that case, we just use the original implementation (based on broadcast and v_readfirstlane). In terms of LD/ST, the original is comparable to the proposed but we have much less code. HPC workloads mostly spill 1 or 2 SGPRs.


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