[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2199-2200
+            (FMLS_ZPmZZ_S PPR:$Pg, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
+  def : Pat<(vselect (nxv2i1 PPR:$Pg), (nxv2f64 (AArch64fma_p (nxv2i1 (AArch64ptrue 31)), (AArch64fneg_mt (nxv2i1 (AArch64ptrue 31)), nxv2f64:$Zn, (nxv2f64 (undef))), ZPR:$Zm, ZPR:$Za)), ZPR:$Za),
+            (FMLS_ZPmZZ_D PPR:$Pg, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
+
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This doesn't effect this patch but just so you know where my head is at, my feeling is that we may end up moving this kind of logic into an AArch64 specific DAG combine.  I say this because between the select, fma and fneg we have three predicates in play and so there's likely to be more cases we can perform the match against plus in the future we're quite likely to have to consider the implications of floating point exceptions which will make predicate analysis even more important.


Repository:
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  https://reviews.llvm.org/D96424/new/

https://reviews.llvm.org/D96424