[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2132-2140
+  // Zd = Za + Zn * Zm
+  def : Pat<(nxv8f16 (AArch64fma_p nxv8i1:$P, nxv8f16:$Zn, nxv8f16:$Zm, nxv8f16:$Za)),
+            (FMLA_ZPZZZ_UNDEF_H $P, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
+  def : Pat<(nxv4f32 (AArch64fma_p nxv4i1:$P, nxv4f32:$Zn, nxv4f32:$Zm, nxv4f32:$Za)),
+            (FMLA_ZPZZZ_UNDEF_S $P, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
+  def : Pat<(nxv2f32 (AArch64fma_p nxv2i1:$P, nxv2f32:$Zn, nxv2f32:$Zm, nxv2f32:$Za)),
+            (FMLA_ZPZZZ_UNDEF_S $P, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
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I might have misread something but these looks like a duplicate of the patterns you've updated just above, which does support the other f16 vector types.  As Dave said, for completeness the other selection blocks will need patterns for nxv4f16 and nxv2f16. 


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-combine.ll:5-7
+; CHECK-LABEL: fmla_s_sel:
+; CHECK: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK: ret
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Generally for these types of tests we use update_llc_test_checks.py to generate the CHECK lines as it aids future updates.


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-combine.ll:194-199
+  %neg_m1 = fsub fast <vscale x 4 x float>
+               shufflevector (<vscale x 4 x float>
+                 insertelement (<vscale x 4 x float> undef, float -0.000000e+00, i32 0),
+                 <vscale x 4 x float> undef,
+                 <vscale x 4 x i32> zeroinitializer),
+               %m1
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It didn't exist when the tests were written but today I think/hope you can use the `fneg` instruction and thus simplify the tests a little.


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  https://reviews.llvm.org/D96424/new/

https://reviews.llvm.org/D96424