[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 323750.
bsmith added a comment.

- Regenerate tests with update_llc_test_checks.py
- Restructure patterns to use a multiclass
- Remove duplicated patterns
- Add missing patterns for more f16 types


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96424/new/

https://reviews.llvm.org/D96424

Files:
  llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
  llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fma-dagcombine.ll
  llvm/test/CodeGen/AArch64/sve-fp-combine.ll
  llvm/test/CodeGen/AArch64/sve-fp.ll

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