[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D96469#2556038 <https://reviews.llvm.org/D96469#2556038>, @t-tye wrote:

> In D96469#2555786 <https://reviews.llvm.org/D96469#2555786>, @rampitec wrote:
>
>> Another question, can we have a shorter name than "cache_policy"? "cpol" maybe? It blows formatting in many places.
>
> What about "cp"? We have "as" I think for address space.

Ack. Also note, it will never appear in asm, only in compiler sources.



================
Comment at: llvm/lib/Target/AMDGPU/SIDefines.h:268-273
+enum CachePolicy {
+  GLC = 1,
+  SLC = 2,
+  DLC = 4,
+  ALL = GLC | SLC | DLC
+};
----------------
t-tye wrote:
> Why is ALL needed? Does the code ever deliberately want to set them all? I would suspect places only even want to set specific bits.
It is used as ~ALL for mask verification.


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