[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIDefines.h:268-273
+enum CachePolicy {
+  GLC = 1,
+  SLC = 2,
+  DLC = 4,
+  ALL = GLC | SLC | DLC
+};
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Why is ALL needed? Does the code ever deliberately want to set them all? I would suspect places only even want to set specific bits.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96469/new/

https://reviews.llvm.org/D96469