[PATCH] D95853: [RISCV] Use whole register load/store for generic load/store.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:183
+    return MCDisassembler::Fail;
+
+  MCRegister Reg;
----------------
craig.topper wrote:
> Can we get the VR register name with RISCV::V0 + RegNo and then convert with getMatchingSuperReg?
Though we might not be able to get to MRI from here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95853/new/

https://reviews.llvm.org/D95853