[PATCH] D95853: [RISCV] Use whole register load/store for generic load/store.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:901
+    llvm_unreachable("Unexpected vector registers!");
+  case RISCV::V0:
+    return RISCV::V0M2;
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Can we use MCRegisterInfo::getMatchingSuperReg to get do this conversion?


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Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:183
+    return MCDisassembler::Fail;
+
+  MCRegister Reg;
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Can we get the VR register name with RISCV::V0 + RegNo and then convert with getMatchingSuperReg?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:181
+      defset list<VTypeInfo> FractionalGroupIntegerVectors = {
       def VI8MF8: VTypeInfo<vint8mf8_t,  vbool64_t,  8, VR, V_MF8>;
       def VI8MF4: VTypeInfo<vint8mf4_t,  vbool32_t,  8, VR, V_MF4>;
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indent these lines?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:215
+      defset list<VTypeInfo> FractionalGroupFloatVectors = {
       def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, VR, V_MF4, f16, FPR16>;
       def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, VR, V_MF2, f16, FPR16>;
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indent these lines


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  https://reviews.llvm.org/D95853/new/

https://reviews.llvm.org/D95853