[PATCH] D95853: [RISCV] Use whole register load/store for generic load/store.

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 8 17:05:18 PST 2021


HsiangKai updated this revision to Diff 322244.
HsiangKai added a comment.

Address @craig.topper's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95853/new/

https://reviews.llvm.org/D95853

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
  llvm/test/CodeGen/RISCV/scalable-vector-struct.ll
  llvm/test/MC/RISCV/rvv/invalid.s

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