[PATCH] D95844: [RISCV] Use a ComplexPattern to merge isel patterns for vector load/store with GPR and FrameIndex addresses.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 1 23:41:07 PST 2021
craig.topper added a comment.
In D95844#2535764 <https://reviews.llvm.org/D95844#2535764>, @rogfer01 wrote:
> I understand it is not a win to apply a similar scheme to the base `RISCVInstrInfo.td` and perhaps F's and D's because we do have an offset available there. Is my understanding correct?
>
> For instance now we have in the base `.td`:
>
> multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
> def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
> def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>;
> def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
> (Inst GPR:$rs1, simm12:$imm12)>;
> def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)),
> (Inst AddrFI:$rs1, simm12:$imm12)>;
> def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
> (Inst AddrFI:$rs1, simm12:$imm12)>;
> }
I didn't realize how many times that is instantiated. We can probably at lest merge patterns 1 and 2 together, and 3 and 4 together. I ideally we could merge all of them with a ComplexPattern that emitted 2 results, but I think that requires changing the "ins" operands for the instructions and some assembly parser changes.
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https://reviews.llvm.org/D95844/new/
https://reviews.llvm.org/D95844
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