[PATCH] D95844: [RISCV] Use a ComplexPattern to merge isel patterns for vector load/store with GPR and FrameIndex addresses.

Roger Ferrer Ibanez via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 1 23:29:28 PST 2021


rogfer01 added a comment.

I understand it is not a win to apply a similar scheme to the base `RISCVInstrInfo.td` and perhaps F's and D's because we do have an offset available there. Is my understanding correct?

For instance now we have in the base `.td`:

  multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
    def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
    def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>;
    def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
              (Inst GPR:$rs1, simm12:$imm12)>;
    def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)),
              (Inst AddrFI:$rs1, simm12:$imm12)>;
    def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
              (Inst AddrFI:$rs1, simm12:$imm12)>;
  }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95844/new/

https://reviews.llvm.org/D95844



More information about the llvm-commits mailing list