[PATCH] D95610: [AMDGPU] Clarify calling conv about inactive lanes

[Tony Tye via Phabricator via llvm-commits]

t-tye requested changes to this revision.
t-tye added inline comments.
This revision now requires changes to proceed.


================
Comment at: llvm/docs/AMDGPUUsage.rst:8242-8262
     * VGPR40-47
       VGPR56-63
       VGPR72-79
       VGPR88-95
       VGPR104-111
       VGPR120-127
       VGPR136-143
----------------
Suggest re-wording to:

```` 
    * VGPR40-47
    * VGPR56-63
    * VGPR72-79
    * VGPR88-95
    * VGPR104-111
    * VGPR120-127
    * VGPR136-143
    * VGPR152-159
    * VGPR168-175
    * VGPR184-191
    * VGPR200-207
    * VGPR216-223
    * VGPR232-239
    * VGPR248-255

       .. note::

          Except the argument registers, the VGPR clobbered and the
          preserved registers are intermixed at regular intervals in
          order to keep a similar ratio independent of the number of
          allocated VGPRs.

    * Lanes of all VGPRs that are inactive at the call site.
````


================
Comment at: llvm/docs/AMDGPUUsage.rst:8259
         registers are intermixed at regular intervals in order to
-        get a better occupancy.*
+        keep a similar ratio independent of the amount of available VGPRs.*
+
----------------
... keep a similar ratio independent of the number of allocated VGPRs.


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https://reviews.llvm.org/D95610