[PATCH] D95610: [AMDGPU] Clarify calling conv about inactive lanes

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne created this revision.
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sebastian-ne added a project: AMDGPU.
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So far, it was not specified what happens with the VGPRs of inactive
lanes when functions are called. This patch explicitely mentions that
the VGPR values of inactive lanes need to be preserved for all
registers.

This describes the current behavior, as only active lanes of registers
are saved to scratch. Also, as the multi-lane nature of VGPRs is not
properly modeled, we cannot determine the live VGPRs from inactive lanes
at calls. So we cannot save them, even if we intended to do so.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95610

Files:
  llvm/docs/AMDGPUUsage.rst


Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -8256,7 +8256,10 @@
 
         *Except the argument registers, the VGPR clobbered and the preserved
         registers are intermixed at regular intervals in order to
-        get a better occupancy.*
+        keep a similar ratio independent of the amount of available VGPRs.*
+
+      Lanes of VGPRs that are inactive for the call must be preserved for all
+      VGPRs.
 
       For the AMDGPU backend, an inter-procedural register allocation (IPRA)
       optimization may mark some of clobbered SGPR and VGPR registers as


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