[PATCH] D95610: [AMDGPU] Clarify calling conv about inactive lanes
Sebastian Neubauer via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 28 06:05:41 PST 2021
sebastian-ne created this revision.
sebastian-ne added reviewers: arsenm, t-tye.
sebastian-ne added a project: AMDGPU.
Herald added subscribers: kerbowa, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
sebastian-ne requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
So far, it was not specified what happens with the VGPRs of inactive
lanes when functions are called. This patch explicitely mentions that
the VGPR values of inactive lanes need to be preserved for all
registers.
This describes the current behavior, as only active lanes of registers
are saved to scratch. Also, as the multi-lane nature of VGPRs is not
properly modeled, we cannot determine the live VGPRs from inactive lanes
at calls. So we cannot save them, even if we intended to do so.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D95610
Files:
llvm/docs/AMDGPUUsage.rst
Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -8256,7 +8256,10 @@
*Except the argument registers, the VGPR clobbered and the preserved
registers are intermixed at regular intervals in order to
- get a better occupancy.*
+ keep a similar ratio independent of the amount of available VGPRs.*
+
+ Lanes of VGPRs that are inactive for the call must be preserved for all
+ VGPRs.
For the AMDGPU backend, an inter-procedural register allocation (IPRA)
optimization may mark some of clobbered SGPR and VGPR registers as
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95610.319846.patch
Type: text/x-patch
Size: 691 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210128/8aa0b583/attachment-0001.bin>
More information about the llvm-commits
mailing list