[PATCH] D95610: [AMDGPU] Clarify calling conv about inactive lanes

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne updated this revision to Diff 320077.
sebastian-ne added a comment.

Reword as suggested


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95610/new/

https://reviews.llvm.org/D95610

Files:
  llvm/docs/AMDGPUUsage.rst


Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -8254,9 +8254,13 @@
       VGPR232-239
       VGPR248-255
 
-        *Except the argument registers, the VGPR clobbered and the preserved
-        registers are intermixed at regular intervals in order to
-        get a better occupancy.*
+        .. note::
+
+          Except the argument registers, the VGPRs clobbered and the preserved
+          registers are intermixed at regular intervals in order to keep a
+          similar ratio independent of the amount of allocated VGPRs.
+
+    * Lanes of all VGPRs that are inactive at the call site.
 
       For the AMDGPU backend, an inter-procedural register allocation (IPRA)
       optimization may mark some of clobbered SGPR and VGPR registers as


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