[PATCH] D77804: [DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64Zbp.ll:1433
+; RV64IB-NEXT:    or a0, a2, a0
+; RV64IB-NEXT:    or a0, a0, a1
 ; RV64IB-NEXT:    ret
----------------
RKSimon wrote:
> Looks like we've defeated the  RISCVISD::GORCI matching code
Running the tests through instcombine also breaks GORCI matching.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804