[PATCH] D77804: [DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64Zbp.ll:1433
+; RV64IB-NEXT:    or a0, a2, a0
+; RV64IB-NEXT:    or a0, a0, a1
 ; RV64IB-NEXT:    ret
----------------
Looks like we've defeated the  RISCVISD::GORCI matching code


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804