[PATCH] D77804: [DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rv64Zbp.ll:1433
+; RV64IB-NEXT:    or a0, a2, a0
+; RV64IB-NEXT:    or a0, a0, a1
 ; RV64IB-NEXT:    ret
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craig.topper wrote:
> RKSimon wrote:
> > Looks like we've defeated the  RISCVISD::GORCI matching code
> Running the tests through instcombine also breaks GORCI matching.
It's also worth noting, the tests that are failing are repeating the same pattern gorc pattern twice, which is redundant. The test was trying to test that we could detect the redundancy. I guess this patch may have seen some of the redundancy?


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  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804