[PATCH] D95422: [RISCV] Copy isUnneededShiftMask from X86.

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

This looks good but it would be nice to have targeted regression tests.



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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:738-739
+bool RISCVDAGToDAGISel::isUnneededShiftMask(SDNode *N, unsigned Width) const {
+  assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
+  const APInt &Val = N->getConstantOperandAPInt(1);
+
----------------
Maybe add an assertion that operand 1 has the appropriate type?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95422/new/

https://reviews.llvm.org/D95422