[PATCH] D95146: [RISCV] Make v extension imply zvamo, zvlsseg

[Simon Cook via Phabricator via llvm-commits]

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The V (vector) extension should enable the zvamo and zvlsseg extensions,
but currently is defined the other way around in TableGen. This updates
the SubtargetFeatures to reverse the inheritence order to be correct.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95146

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

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