[PATCH] D95146: [RISCV] Make v extension imply zvamo, zvlsseg

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Doesn't this mean that if you only enable zvlsseg, you'll be able to use the instruction in that extension but not the vsetvli instruction that you need to program the VL register?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95146/new/

https://reviews.llvm.org/D95146