[llvm] b8921af - [RISCV] Update V instructions constraints to conform to v1.0
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 21 09:16:18 PST 2021
Author: Hsiangkai Wang
Date: 2021-01-22T01:15:55+08:00
New Revision: b8921af63b0d746606f2482f3a020ea7cd316cd2
URL: https://github.com/llvm/llvm-project/commit/b8921af63b0d746606f2482f3a020ea7cd316cd2
DIFF: https://github.com/llvm/llvm-project/commit/b8921af63b0d746606f2482f3a020ea7cd316cd2.diff
LOG: [RISCV] Update V instructions constraints to conform to v1.0
Upgrade RISC-V V extension to v1.0-08a0b46.
Update instruction constraints to conform to v1.0.
Differential Revision: https://reviews.llvm.org/D93612
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/add.s
llvm/test/MC/RISCV/rvv/convert.s
llvm/test/MC/RISCV/rvv/invalid.s
llvm/test/MC/RISCV/rvv/shift.s
llvm/test/MC/RISCV/rvv/sub.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index ea867c549e64..7be74b79d99b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -64,22 +64,21 @@ def VMConstraint : RISCVVConstraint<0b100>;
// register is being written with a mask value (e.g., comparisons) or the
// scalar result of a reduction.
//
-// * Widening: The destination vector register group cannot overlap a source
-// vector register group of a
diff erent EEW
+// * Widening: The destination EEW is greater than the source EEW, the source
+// EMUL is at least 1. The destination vector register group cannot overlap
+// with the source vector register groups besides the highest-numbered part of
+// the destination register group.
//
-// * Narrowing: The destination vector register group cannot overlap the
-// first source vector register group
+// * Narrowing: The destination EEW is smaller than the source EEW. The
+// destination vector register group cannot overlap with the source vector
+// register groups besides the lowest-numbered part of the source register
+// group.
//
-// * For vadc and vsbc, an illegal instruction exception is raised if the
-// destination vector register is v0.
+// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the
+// source register and, if masked, cannot overlap the mask register ('v0').
//
-// * For vmadc and vmsbc, an illegal instruction exception is raised if the
-// destination vector register overlaps a source vector register group.
-//
-// * viota: An illegal instruction exception is raised if the destination
-// vector register group overlaps the source vector mask register. If the
-// instruction is masked, an illegal instruction exception is issued if the
-// destination vector register group overlaps v0.
+// * viota: The destination register cannot overlap the source register and,
+// if masked, cannot overlap the mask register ('v0').
//
// * v[f]slide[1]up: The destination vector register group for vslideup cannot
// overlap the source vector register group.
@@ -96,12 +95,6 @@ def WidenW : RISCVVConstraint<!or(VS1Constraint.Value,
VMConstraint.Value)>;
def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value,
VMConstraint.Value)>;
-def Narrow : RISCVVConstraint<!or(VS2Constraint.Value,
- VMConstraint.Value)>;
-def NarrowCvt : RISCVVConstraint<!or(VS2Constraint.Value,
- VMConstraint.Value)>;
-def Vmadc : RISCVVConstraint<!or(VS2Constraint.Value,
- VS1Constraint.Value)>;
def Iota : RISCVVConstraint<!or(VS2Constraint.Value,
VMConstraint.Value)>;
def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 7d3f5071ee9e..e7962b921278 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -553,15 +553,15 @@ defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
// Vector Bitwise Logical Instructions
defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
@@ -581,10 +581,10 @@ defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>;
// The destination vector register group cannot overlap the first source
// vector register group (specified by vs2). The destination vector register
// group cannot overlap the mask register if used, unless LMUL=1.
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
+let Constraints = "@earlyclobber $vd" in {
defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+} // Constraints = "@earlyclobber $vd"
def : InstAlias<"vncvt.x.x.w $vd, $vs$vm",
(VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
@@ -731,10 +731,10 @@ defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>;
defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>;
// Vector Narrowing Fixed-Point Clip Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
+let Constraints = "@earlyclobber $vd" in {
defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">;
defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+} // Constraints = "@earlyclobber $vd"
} // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in {
@@ -859,7 +859,7 @@ defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
// Narrowing Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt in {
+let Constraints = "@earlyclobber $vd" in {
defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>;
defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>;
defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
@@ -868,7 +868,7 @@ defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>;
defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt
+} // Constraints = "@earlyclobber $vd"
} // Predicates = [HasStdExtV, HasStdExtF]
let Predicates = [HasStdExtV] in {
@@ -950,17 +950,14 @@ def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
"vfirst.m", "$vd, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
// vmsbf.m set-before-first mask bit
defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
-
// vmsif.m set-including-first mask bit
defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
-
// vmsof.m set-only-first mask bit
defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
-
// Vector Iota Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
@@ -1000,12 +997,9 @@ let Predicates = [HasStdExtV] in {
// Vector Slide Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
-defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
-
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
} // Predicates = [HasStdExtV]
diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s
index f588d90a9c57..18bd10fee3f8 100644
--- a/llvm/test/MC/RISCV/rvv/add.s
+++ b/llvm/test/MC/RISCV/rvv/add.s
@@ -146,6 +146,18 @@ vadc.vvm v8, v4, v20, v0
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a 40 <unknown>
+vadc.vvm v4, v4, v20, v0
+# CHECK-INST: vadc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 02 4a 40 <unknown>
+
+vadc.vvm v8, v4, v8, v0
+# CHECK-INST: vadc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 44 40 <unknown>
+
vadc.vxm v8, v4, a0, v0
# CHECK-INST: vadc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x40]
@@ -164,6 +176,18 @@ vmadc.vvm v8, v4, v20, v0
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a 44 <unknown>
+vmadc.vvm v4, v4, v20, v0
+# CHECK-INST: vmadc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 02 4a 44 <unknown>
+
+vmadc.vvm v8, v4, v8, v0
+# CHECK-INST: vmadc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 44 44 <unknown>
+
vmadc.vxm v8, v4, a0, v0
# CHECK-INST: vmadc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x44]
diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s
index 0fadd888b8c2..7944f84bc8ed 100644
--- a/llvm/test/MC/RISCV/rvv/convert.s
+++ b/llvm/test/MC/RISCV/rvv/convert.s
@@ -173,6 +173,12 @@ vfncvt.xu.f.w v8, v4, v0.t
# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
# CHECK-UNKNOWN: 57 14 48 48 <unknown>
+vfncvt.xu.f.w v4, v4, v0.t
+# CHECK-INST: vfncvt.xu.f.w v4, v4, v0.t
+# CHECK-ENCODING: [0x57,0x12,0x48,0x48]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 12 48 48 <unknown>
+
vfncvt.xu.f.w v8, v4
# CHECK-INST: vfncvt.xu.f.w v8, v4
# CHECK-ENCODING: [0x57,0x14,0x48,0x4a]
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index fb7b4a0378e1..9763dc07d12b 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -133,78 +133,6 @@ vslide1up.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0
-vnsrl.wv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4
-
-vnsrl.wx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0
-
-vnsrl.wi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsrl.wi v2, v2, 31
-
-vnsra.wv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4
-
-vnsra.wx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0
-
-vnsra.wi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsra.wi v2, v2, 31
-
-vnclipu.wv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4
-
-vnclipu.wx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0
-
-vnclipu.wi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclipu.wi v2, v2, 31
-
-vnclip.wv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4
-
-vnclip.wx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0
-
-vnclip.wi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclip.wi v2, v2, 31
-
-vfncvt.xu.f.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2
-
-vfncvt.x.f.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2
-
-vfncvt.f.xu.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2
-
-vfncvt.f.x.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2
-
-vfncvt.f.f.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2
-
-vfncvt.rod.f.f.w v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2
-
vrgather.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t
@@ -589,14 +517,6 @@ vadc.vvm v0, v2, v4, v0
# CHECK-ERROR: The destination vector register group cannot be V0.
# CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0
-vmadc.vvm v2, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0
-
-vmadc.vvm v4, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0
-
vadd.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t
@@ -652,3 +572,11 @@ vzext.vf2 v0, v1, v0.t
vid.v v0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vid.v v0, v0.t
+
+vnsrl.wv v0, v4, v20, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vnsrl.wv v0, v4, v20, v0.t
+
+vfncvt.xu.f.w v0, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfncvt.xu.f.w v0, v4, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s
index 27d40a57a84b..a4fa8a7bfc8b 100644
--- a/llvm/test/MC/RISCV/rvv/shift.s
+++ b/llvm/test/MC/RISCV/rvv/shift.s
@@ -122,6 +122,12 @@ vnsrl.wv v8, v4, v20, v0.t
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a b0 <unknown>
+vnsrl.wv v4, v4, v20, v0.t
+# CHECK-INST: vnsrl.wv v4, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x02,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 02 4a b0 <unknown>
+
vnsrl.wv v8, v4, v20
# CHECK-INST: vnsrl.wv v8, v4, v20
# CHECK-ENCODING: [0x57,0x04,0x4a,0xb2]
diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s
index 99b0c7a1e60f..9b66677a34ab 100644
--- a/llvm/test/MC/RISCV/rvv/sub.s
+++ b/llvm/test/MC/RISCV/rvv/sub.s
@@ -158,6 +158,18 @@ vsbc.vvm v8, v4, v20, v0
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a 48 <unknown>
+vsbc.vvm v4, v4, v20, v0
+# CHECK-INST: vsbc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 02 4a 48 <unknown>
+
+vsbc.vvm v8, v4, v8, v0
+# CHECK-INST: vsbc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 44 48 <unknown>
+
vsbc.vxm v8, v4, a0, v0
# CHECK-INST: vsbc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x48]
@@ -170,6 +182,18 @@ vmsbc.vvm v8, v4, v20, v0
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a 4c <unknown>
+vmsbc.vvm v4, v4, v20, v0
+# CHECK-INST: vmsbc.vvm v4, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x02,0x4a,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 02 4a 4c <unknown>
+
+vmsbc.vvm v8, v4, v8, v0
+# CHECK-INST: vmsbc.vvm v8, v4, v8, v0
+# CHECK-ENCODING: [0x57,0x04,0x44,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 44 4c <unknown>
+
vmsbc.vxm v8, v4, a0, v0
# CHECK-INST: vmsbc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x4c]
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