[PATCH] D94903: [RISCV] Implement vlxseg intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:510
 
+  // For index segment load
+  // Input: (pointer, index, vl)
----------------
index->indexed


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Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:517
+                    [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
+  // For index segment load with mask
+  // Input: (maskedoff, pointer, index, mask, vl)
----------------
index->indexed


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Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:970
     defm vlsseg # nf : RISCVSSegLoad<nf>;
+    // In v1.0, it should be vloxseg.
+    defm vlxseg # nf : RISCVISegLoad<nf>;
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Make this a FIXME or TODO


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2775
 defm PseudoVLSSEG : VPseudoSSegLoad;
+// In v1.0, it should be PseudoVLOXSEG.
+defm PseudoVLXSEG : VPseudoISegLoad;
----------------
Make this a FIXME or TODO


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94903/new/

https://reviews.llvm.org/D94903