[PATCH] D94903: [RISCV] Implement vlxseg intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 317752.
HsiangKai added a comment.

Add test cases for rv32. It does not contain all combinations of vlxseg due to the revision will be too large to upload.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94903/new/

https://reviews.llvm.org/D94903

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vlxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlxseg-rv64.ll