[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 11 20:58:37 PST 2021

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craig.topper added a comment.

I don't think I ever did anything more with this. @lebedev.ri did you want to pick this up?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66571/new/

https://reviews.llvm.org/D66571

Previous message: [PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask
Next message: [PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask
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