[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

Tue Jan 12 02:24:13 PST 2021

lebedev.ri added a comment.

In D66571#2491979 <https://reviews.llvm.org/D66571#2491979>, @craig.topper wrote:

> I don't think I ever did anything more with this. @lebedev.ri did you want to pick this up?

I wanted to, and to put this into DAGCombiner under target hooks,
but i thought about doing that after D62100 <https://reviews.llvm.org/D62100>, which is stuck due to AArch64 failures to form `ubfx`.
But now that D62100 <https://reviews.llvm.org/D62100> is happening in instcombine, i'm not so sure we need it?

So i guess i can try picking this up.

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https://reviews.llvm.org/D66571