[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 11 12:42:20 PST 2021

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RKSimon added a comment.
Herald added a subscriber: pengfei.

@craig.topper Whatever happened to this patch? It still looks useful.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66571/new/

https://reviews.llvm.org/D66571

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Next message: [PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask
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