[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi Serge, would it make sense to use a `Pseudo` for those specific cases with a custom inserter?

This way you could have `PseudoCSRW` and `PseudoCSRWI` (it looks to me you do not need the other cases, did I get that right?) that you can use in the patterns. Then you can expand them to the existing MachineInstructions `CSRRW`, `CSRRWI`, respectively (hope I didn't get the names wrong), that use `X0` as the destination register in `RISCVTargetLowering::EmitInstrWithCustomInserter`.

I understand your concern with `X0` potentially defining a false write dependency, but I too understand like that we should fix any case in LLVM where constant registers are not handled correctly.


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https://reviews.llvm.org/D90853