[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added a comment.

In D90853#2399577 <https://reviews.llvm.org/D90853#2399577>, @jrtc27 wrote:

> In D90853#2399517 <https://reviews.llvm.org/D90853#2399517>, @sepavloff wrote:
>
>> , fake writes to X0 would create false output dependencies, which would require specific treatment. Using instructions without output is a natural way to represent such cases.
>
> LLVM knows it’s a constant register. The correct thing to do IMO is fix any places in LLVM that don’t account for constant registers, if there are any, and then have a generic solution, rather than try and work around any deficiencies by adding special cases to backends every single time it comes up.

The fact that `X0` is used in destination register field of an instruction to produce write-only variant is peculiarity of RICSV encoding.  It does not mean that `X0` is defined by the instruction. DAG is a higher layer it tries to abstracts from particular ISA. Results of a DAG node are treated much like results of function calls. So write-only CSR instructions should be represented by different nodes in DAG because they have different number of produced values.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90853/new/

https://reviews.llvm.org/D90853