[PATCH] D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR

Dávid Bolvanský via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Jan 2 07:45:17 PST 2021

Previous message: [PATCH] D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax
Next message: [PATCH] D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

xbolva00 added a comment.
Herald added a subscriber: pengfei.

Reping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87464/new/

https://reviews.llvm.org/D87464

Previous message: [PATCH] D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax
Next message: [PATCH] D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list